The present invention relates generally to a piecewisely-controlled tri-state output buffer, and more particularly to a piecewisely-controlled tri-state output buffer with at least two PMOS (P-channel Metal-Oxide Semiconductor) and at least two NMOS (N-channel Metal-Oxide Semiconductor) transistors, which has the advantages of high speed and low output current.
At present, typical electronic logic devices which are commonly used to implement digital electronic circuits include bipolar TTL (Transistor-Transistor Logic) and CMOS (Complementary Metal-Oxide Semiconductor) ICs (Integrated Circuits). In comparison, these two kinds of commonly-used basic logic devices have different characteristics. For example, TTL devices have relatively short signal delay times, and thus have higher processing speed. On the other hand, CMOS devices have longer signal delay times, and thus have lower processing speed, but CMOS devices also have lower power consumption requirement and tolerate a wider power-supply voltage range than do TTL devices. Basically, the power-supply voltage range of CMOS devices may be from about 3V up to 20V DC. If the processing speed is not very important, a lower operating voltage can be used to reduce power consumption. If high processing speed is required, the operating voltage must be increased. In the latter case, power consumption will also be increased.
The power-supply voltage range of TTL devices is relatively narrow, e.g. from about 4.5V to 7V DC. However, the processing speed of TTL devices is far faster than that of CMOS devices, although the power consumption of TTL devices is far higher. Futhermore, the fan-out capability of TTL devices is better than that of CMOS devices, i.e. a single output of a TTL device can drive more inputs than can a single output of a CMOS device.
Due to the limitations of basic physical properties, TTL and CMOS devices inherently have opposite advantages and drawbacks. The choices of power consumption, processing speed, and fan-out capability depend on application requirements, but as a general case, higher speed, lower power consumption, and larger fan-out capability are preferred. In order to achieve optimal integrated circuits, many approaches have been proposed in this art to decrease the power consumption of TTL devices, or to enhance the speed and fan-out capability of CMOS devices.
According to CMOS technology, if a CMOS IC is intended to reach the same speed performance as the F series of TTL devices, large-sized MOS transistors must be used. This will however result in relatively large output current, and thus relatively high power consumption. Therefore, if an output buffer only utilizes a pair of PMOS and NMOS transistors, it is hard to obtain high speed, and to keep the low output current characteristic of CMOS devices.